The present invention relates generally to code conversion, and more particularly to conversion of recording codes which are used when digital data is recorded in a digital VTR, an optical disc storage, a magnetic disc storage and the like or which are used when digital data is transmitted via a transmission system.
When digital data is recorded onto a recording medium in high density, or transmitted via any transmission system, (1, 7) code is conventionally used. FIG. 11 shows an example of a conventional (1, 7) code conversion rule table.
This (1, 7) code conversion rule table includes 7 kinds of correspondence relations between data bits and channel bits, and shows that the following code conversion is performed. That is, data bits xe2x80x9c00xe2x80x9d are converted to channel bits xe2x80x9c00Xxe2x80x9d, and, similarly, xe2x80x9c01xe2x80x9d are converted to xe2x80x9c010xe2x80x9d, xe2x80x9c10xe2x80x9d are converted to xe2x80x9c10Xxe2x80x9d, xe2x80x9c1100xe2x80x9d are converted to xe2x80x9c000010xe2x80x9d, xe2x80x9c1101xe2x80x9d are converted to xe2x80x9c00000Xxe2x80x9d, xe2x80x9c1110xe2x80x9d are converted to xe2x80x9c100010xe2x80x9d, and xe2x80x9c1111xe2x80x9d are converted to xe2x80x9c10000Xxe2x80x9d. In this rule table, a symbol X designates an indefinite bit, and becomes xe2x80x9c1xe2x80x9d when the next channel bit following the indefinite bit is xe2x80x9c0xe2x80x9d and becomes xe2x80x9c0xe2x80x9d when the next channel bit following the indefinite bit is xe2x80x9c1xe2x80x9d. Also, recording or transmission of the (1, 7) code data is performed by using NRZI signal system. That is, the channel bits are sequentially disposed and xe2x80x9c1xe2x80x9d is converted to inversion of a signal and xe2x80x9c0xe2x80x9d is converted to non-inversion of the signal to record or transmit them.
The conventional (1, 7) recording code has the following characteristics. That is, at channel bit level, number of xe2x80x9c0xe2x80x9d existing between xe2x80x9c1xe2x80x9d and adjacent xe2x80x9c1xe2x80x9d is equal to or larger than 1 and equal to or smaller than 7. Therefore, when digital data is recorded and reproduced by using NRZI signal system, number of non-inversion bits existing between adjacent inversion bits can be equal to or larger than 1 bit and equal to or smaller than 7 bits. Thus, when a clock period of a signal after modulation or encoding is Ts, minimum interval between inversions becomes 2Ts and maximum interval between inversions becomes 8Ts. In practice, however, original bit number is multiplied by 1.5, because data bits having, for example, 2 bits are converted into channel bits having 3 bits. Therefore, with respect to a period Tb before modulation, timing relation becomes as follows.
Tmin=1.33Tb (minimum interval between inversions)
Tmax=5.33Tb (maximum interval between inversions)
Twin=0.67Tb (width of detection window)
The (1, 7) code has the characteristics mentioned above, and parameters Tmin, Twin, Tmin*Twin are relatively large so that a recording system using the (1, 7) code is suitable for high density recording. However, the conventional (1, 7) code has the following disadvantages.
In case code conversion is performed according to the (1, 7) code conversion rule table shown in FIG. 11, consider a condition in which data bits xe2x80x9c10xe2x80x9d and data bits xe2x80x9c01xe2x80x9d are alternately supplied. That is, data
xe2x80x9c1001100110011001 . . . xe2x80x9d
is continuously inputted. In this case, channel bits become a repetition of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. That is, the channel bits become as follows.
xe2x80x9c101010101010101010101010 . . . xe2x80x9d
This is a continuation of 2Ts patterns. Continuation of the 2Ts patterns is a pattern having maximum repetition frequency in the (1, 7) codes. If the 2Ts patterns continue in a data reproducing system, a signal level of a reproduced data reduces and a PLL (phase-locked loop) circuit used in the reproducing system tends to be out of synchronization. Therefore, it is necessary to avoid continuous occurrence of the 2Ts patterns for a long time as much as possible. However, in the conventional (1, 7) code, such continuous occurrence of the 2Ts patterns was inevitable.
In order to reduce bad influence of out of synchronization of the PLL circuit to minimum, conventionally, there is known a technique of periodically inserting a re-synchronizing signals into a recording data. For example, see Japanese patent laid-open publication No. 6-195893. However, since this technique is not a technique for avoiding occurrence of 2Ts patterns continuously for a long time, there was a problem that, depending on the locations of insertion of the re-synchronizing signals, the 2Ts patterns were produced continuously for a long time, thereby causing out of synchronization of the PLL circuit.
Therefore, it is an object of the present invention to obviate disadvantages of the conventional recording codes.
It is another object of the present invention to avoid continuous and long time occurrence of 2Ts patterns in recording codes.
It is still another object of the present invention to realize stable operation of a PLL circuit when reproducing digital data recorded onto a recording medium or transmitted via a transmission system.
It is still another object of the present invention to effectively decrease DC component of recording codes and to reduce bad influence caused by signal jittering.
It is still another object of the present invention to improve reliability of digital data storage or digital data transmission.
According to an aspect of the present invention, there is provided a method for encoding recording codes wherein data bits are encoded into channel bits. The method comprises: allotting respective channel bits xe2x80x9c00Xxe2x80x9d, xe2x80x9c010xe2x80x9d and xe2x80x9c10Xxe2x80x9d to 3 patterns of data bits among 4 patterns of data bits having 2 bits, where X designates an indefinite bit which becomes xe2x80x9c1xe2x80x9d when the channel bit succeeding the indefinite bit is xe2x80x9c0xe2x80x9d and becomes xe2x80x9c0xe2x80x9d when the channel bit succeeding the indefinite bit is xe2x80x9c1xe2x80x9d ; allotting channel bits xe2x80x9c000010xe2x80x9d, xe2x80x9c00000Xxe2x80x9d, xe2x80x9c100010xe2x80x9d and xe2x80x9c10000Xxe2x80x9d to 4 patterns of data bits having 4 bits which are a combination of two bits having a remaining one pattern among the 4 pattern of the data bits having 2 bits and additional two bits; and allotting channel bits xe2x80x9c100000010xe2x80x9d as a special pattern to data bits having 6 bits which are the continuation of alternate 3 patterns of data bits to be encoded to channel bits xe2x80x9c010xe2x80x9d and data bits to be encoded to channel bits xe2x80x9c10Xxe2x80x9d.
According to another aspect of the present invention, there is provided a method for decoding channel bits encoded by the method mentioned above. In this method, from channel bits to be decoded having 3 bits, channel bits having 6 bits preceding the channel bits to be decoded and channel bits having 5 bits succeeding the channel bits to be decoded, decoded data bits having 2 bits are obtained.
According to still another aspect of the present invention, there is provided a method for encoding recording codes wherein data bits are encoded into channel bits. This method comprises: allotting respective channel bits xe2x80x9c00Xxe2x80x9d, xe2x80x9c010xe2x80x9d and xe2x80x9c10Xxe2x80x9d to 3 patterns of data bits among 4 pattern of data bits having 2 bits, where X designates an indefinite bit which becomes xe2x80x9c1xe2x80x9d when the channel bit succeeding the indefinite bit is xe2x80x9c0xe2x80x9d and becomes xe2x80x9c0xe2x80x9d when the channel bit succeeding the indefinite bit is xe2x80x9c1xe2x80x9d; allotting channel bits xe2x80x9c000010xe2x80x9d, xe2x80x9c00000Xxe2x80x9d, xe2x80x9c100010xe2x80x9d and xe2x80x9c10000Xxe2x80x9d to 4 pattern of data bits having 4 bits which are a combination of two bits having a remaining one pattern among said 4 pattern of the data bits having 2 bits and additional two bits; and allotting channel bits xe2x80x9c000000010xe2x80x9d or xe2x80x9c100000010xe2x80x9d as a special pattern to data bits having 6 bits which are the continuation of alternate 3 patterns of data bits to be encoded to channel bits xe2x80x9c010xe2x80x9d and data bits to be encoded to channel bits xe2x80x9c10Xxe2x80x9d, one of the channel bits xe2x80x9c000000010xe2x80x9d and xe2x80x9c100000010xe2x80x9d being selected according to a predetermined criterion. By this method, DC component of the recording codes can be further decreased and bad influence by signal jittering can be reduced.
According to still another aspect of the present invention, when, for example, DC component of an encoded digital signal is to be removed, it is possible to select one pattern of channel bits, such that DSV (Digital Sum Value) of an encoded data is minimized, among a plurality patterns of channel bits allotted to one kind of data bits. Also, in order to remove DC component and to enhance immunity against signal jittering, it is possible to select one pattern of channel bits such that DSV of an encoded data is minimized, while satisfying limitation of maximum interval between inversions.
According to still another aspect of the present invention, there is provided a method for inserting synchronization signals into a series of data bits encoded by the method as mentioned above. In the method, a synchronization signal which includes a bit pattern xe2x80x9c10000000100000001xe2x80x9d, which ends with xe2x80x9c010xe2x80x9d and which starts from xe2x80x9c010xe2x80x9d is inserted into the series of data bits.
According to still another aspect of the present invention, there is provided a method for inserting synchronization signals, by which method, it is possible to surely determine the number of the synchronization signal block in a sector of recording codes when the sector comprises a plurality of synchronization signal blocks each including data signal and a synchronization signal. In this method, synchronization signals having different patterns are inserted into respective synchronization signal blocks of the plurality of synchronization signal blocks.
According to still another aspect of the present invention, there is provided a method for inserting synchronization signals by which DC component can be removed. In this method, a plurality of synchronization signals having predetermined different patterns are prepared and, when a synchronization signal is inserted into a synchronization signal block, the synchronization signal is selected so as to minimize DSV of the synchronization signal block.
According to still another aspect of the present invention, there is provided a method for inserting synchronization signals by which DC component can be reduced and immunity against signal jittering can be improved. In this method, when a sector of recording codes comprises a plurality of synchronization signal blocks each including data signal and a synchronization signal, a plurality of synchronization signals having predetermined different patterns are prepared corresponding to each synchronization signal block, and, when a synchronization signal is inserted into a synchronization signal block, the synchronization signal is selected so as to minimize DSV of the synchronization signal block among the plurality of synchronization signals prepared for the synchronization signal block.